زبان‌های توصیف سخت‌افزار کامپیوتر و کاربردهای آن‌ها ۲۰۱۴
Computer Hardware Description Languages and their Applications 2014

1. Front Cover

2. Computer Hardware Description Languages and Their Applications

3. Copyright Page

4. Table of Contents

5. Preface

6. Conference Organization

7. “Real Time Distributed Systems (invited presentation)” Mario R. Barbacci, Carnegie Mellon University

8. Real-time Distributed Systems

9. Session : BDD-based Design and Analysis Techniques chair: Luc Claesen

10. Verification of the Futurebus+ Cache Coherence Protocol*

11. Chapter 03.”Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation”

12. Chapter 04.”Hardware- Verification using First Order BDDs “

13. Session: HDL-based Design Methods chair: Franz Rammig

14. Chapter 05.”HW/SW Co-Design with PRAMs Using CoDES”

15. Chapter 06.”Prevail-DM: A Framework-Based Environment for Formal Hardware Verification “

16. Chapter 07.”Better Verification Through Symmetry”

17. Session: Synthesis and Verification chair: Mario Barbacci

18. Chapter 08.”A Rewriting Based Method for the Formal Verification of Microprocessors”

19. Chapter 09.”Reasoning about the VHDL Standard Logic Package Signal Data Type “

20. Chapter 10.”An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area”

21. Chapter 11.”Integrating Boolean Verification with Formal Derivation”

22. Chapter 12.”Automated High-level Verification Against Clocked Algorithmic Specifications”

23. Chapter 13.”The Backward Walk Approach in FSM Verification”

24. Invited Presentation : Automatic Verification of Sequential Circuit Designs Edmund M. Clarke, Carnegie Mellon University

25. Automatic Verification of Sequential Circuit Designs

26. Session: Protocol Specification chair: Ed Cerny

27. Chapter 14.”Toward a Basis for Protocol Specification and Process Decomposition “

28. Chapter 15.”Integrating SDL and VHDL for System-Level Hardware Design”

29. Session:Formal Reasoning about Regular Structures chair: Carlos Delgado Kloos

30. Chapter 16. Reasoning About Array Structures Using a Dependently Typed Logic

31. Chapter 17.”VHDL Description and Formal Verification of Systolic Multipliers”

32. Chapter 18.Transformational Rewriting with Ruby

33. Session: High Level Synthesis chair: Flavio Wagner

34. Chapter 19.”A Representation for the Binding of RT-Component Functionality to HDL Behavior”

35. Chapter 20.”Performance Specification and Measurement”

36. Chapter 21.”Automatic Synthesis of Sequential Synchronizations”

37. Session:Design Capture chair: Edmund M. Clarke

38. Chapter 22.”Specifying Hardware Systems in LOTOS”

39. Chapter 23.”HML: A Hardware Description Language Based on Standard ML”

40. Chapter 24.”An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems”

41. Chapter 25.”Linking System Design Tools and Hardware Design Tools

42. Chapter 26.”Automatic VHDL Model Generation System”

43. Chapter 27.Automatic VHDL Model Generation System

44. Chapter 28.”The Modeler’s Assistant: A CAD Tool for Behavioral Model Development”

45. Chapter 29.”Insulin: An Instruction Set Simulation Environment”

46. “Specification languages for communication protocols (invited presentation)”

47. Session: Timing Specifications in HDLs chair: John Brzozowski

48. Chapter 30.”Integrating Behavior and Timing in Executable Specifications”

49. Chapter 31.”ESP: An Executable Specification Language for Mixed Timing Control Circuits “

50. Session:Textual and Graphical HDLs chair: Robert Hum

51. Chapter 32.”UDL/I version Two: A New Horizon of HDL Standards”

52. Chapter 33.”Verilog HDL Modeling Styles for Formal Verification”

53. Chapter 34.”A Visual Hardware Description Language “

54. Chapter 35.”Textual/Graphical Design Concept-Level Synthesis”

55. Sessions : VHDL

56. Chapter 36.”System-Level Specification and Design Using VHDL: A Case Study”

57. Chapter 37.”A Denotational Definition of the VHDL Simulation Kernel”

58. Chapter 38.”Checking DFT Rules with a VHDL Simulator”

59. Chapter 39.”Parameterized VHDL entities for the simulation of hybrid circuits”

60. Chapter 40.”Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models”

61. Chapter 41.”Analog-VHDL: As an application, a real example”