زبان‌های توصیف سخت‌افزار رایانه و کاربردهای آن‌ها ۲۰۱۴
Computer Hardware Description Languages and their Applications 2014

1. Front Cover

2. Computer Hardware Description Languages and their Applications

3. Copyright Page

4. Table of Contents

5. PREFACE

6. Chapter 1. SOME ISSUES IN HDL–BASED BEHAVIOR MODELLING

7. Chapter 2. From a HDL Description to Formal Proof Systems: Principles and Mechanization

8. Chapter 3. Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO

9. Chapter 4. A METHODOLOGY FOR PROVING CORRECTNESS OF PARAMETERIZED HARDWARE MODULES IN HOL

10. Chapter 5. An Exercise in VHDL Timing Back-Annotation

11. Chapter 6. Behavioral Level Modeling of Gate Level Loading Effects

12. Chapter 7. Putting Different Simulation Models Together -The Simulation Configuration Language VHDL/S

13. Chapter 8. High Level Specification and Synthesis of Sequential Logic Modules

14. Chapter 9. Fully generic description of hardware in VHDL

15. Chapter 10. Integrating Hardware Verification with CHDLs

16. Chapter 11. SpecCharts : A Language for System Level Synthesis

17. Chapter 12. Description Methods of CHDL for Redesign Methods

18. Chapter 13. Declarative languages – still a long way to go

19. Chapter 14. Abstraction Mechanisms for Hardware Verification: Formalisation in a Process Algebra

20. Chapter 15. Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications

21. Chapter 16. A Method for Symbolic Verification of Synchronous Circuits

22. Chapter 17. OPERATION / EVENT GRAPHS: A Design Representation for Timing Behavior

23. Chapter 18. A New Timed Petri Net Model for Hardware Representation

24. Chapter 19. An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory

25. Chapter 20. Experience in Designing Formally Verifiable HDL’s

26. Chapter 21. VHDL Extensions Needed for Synthesis and Design

27. Chapter 22. Hierarchical Action Refinement: A Methodology for Compiling Asynchronous Circuits from a Concurrent HDL

28. Chapter 23. EDISYN: A Language-Based Editor for High-level Synthesis

29. Chapter 24. A Constraint-Driven Approach to Configuration Binding in an Object-Oriented VHDL CAD System

30. Chapter 25. A User Interface for VHDL Behavioral Modeling

31. Chapter 26. VHDL Semantics for Behavioral Test Generation

32. Chapter 27. Using a VHDL description to generate hardware test

33. Chapter 28. Functional Tests for Hardware Derived from VHDL Description